1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming an air gap adjacent a bottom source/drain region of a vertical transistor device and the resulting device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, vertical transistors, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1 is a simplistic and schematic depiction of an illustrative prior art vertical transistor device 10. In general, the vertical transistor 10 comprises a generally vertically oriented channel semiconductor structure 12A that extends upward from a front surface 12S of a semiconductor substrate 12. As indicated in the right-hand portion of FIG. 1, the semiconductor structure 12A may have a variety of different configurations when viewed from above, e.g., circular, rectangular, square, etc., and it has an outer perimeter 12P. The device 10 further comprises a channel region 13, a gate-all-around (GAA) gate structure 14 that is positioned around the perimeter 12P of the semiconductor structure 12A, a bottom source/drain (S/D) region 16, a top S/D region 18, a bottom spacer 15B, and a top spacer 15T. Also depicted is an illustrative bottom contact 20 that is conductively coupled to the bottom S/D region 16 and a top contact 22 that is conductively coupled to the top S/D region 18. In the depicted example, the gate structure 14 comprises a gate insulation layer 14A and a conductive gate electrode 14B. The materials of construction for the components of the device 10 may vary depending upon the particular application. The gate structure 14 may be manufactured using well-known gate first or replacement gate manufacturing techniques.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years, particularly the channel length of transistor devices. As a result of the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the “packing density,” i.e., the number of transistor devices per unit area, in such products has also increased during that time. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections or “wiring arrangement” for the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured. Accordingly, the various electrical connections that constitute the overall wiring pattern for the integrated circuit product are formed in one or more additional stacked so-called “metallization layers” that are formed above the device level of the product. These metallization layers are typically comprised of layers of insulating material with conductive metal lines or conductive vias formed in the layers of material. The first metallization layer in an integrated circuit product is typically referred to as the “M1” layer (or in some cases the “M0” layer), while the conductive vias that are used to establish electrical connection between the M1 layer and lower level conductive structures (explained more fully below) are typically referred to as “V0” vias.
A plurality of device-level contacts is formed so as to establish electrical connection with the metallization layers and the actual semiconductor device, i.e., the transistor. With respect to the formation of a vertical transistor device, such device level contacts would include the schematically depicted top source/drain contact (CA) 22 that is conductively coupled to the top S/D region 18, the schematically depicted bottom source/drain contact (CA) 20 that is conductively coupled to the bottom source/drain (S/D) region 16 and a gate contact (CB) (not shown) that is conductively coupled to the gate structure 14. The CA contacts and the CB contact are typically a uniform body of metal, e.g., tungsten, and may also include one or more metallic barrier layers (not shown) positioned between the uniform body of metal and a surrounding insulating material. With reference to FIG. 1, the spacers 15B, 15T are typically made of silicon nitride which has a relatively high k value of, e.g., about 7-8. As a result of the physical configuration of the vertical transistor 10, a gate-to-bottom S/D capacitor is defined, wherein the gate electrode 14B functions as one of the conductive plates of the capacitor and the bottom source/drain (S/D) region 16 functions as the other conductive plate of the capacitor and the bottom spacer 15B is positioned between the two conductive plates. This gate-to-bottom S/D capacitor is parasitic in nature in that this capacitor must charge and discharge every time the transistor device 10 is turned on and off, all of which results in delaying the switching speed of the device 10. Device designers have made efforts to reduce the parasitic gate-to-bottom S/D capacitor. For example, some process flows have been developed for forming the spacers 15T, 15B of a material having a lower k value than that of silicon nitride so as to reduce the capacitance.
The present disclosure is directed to various novel methods of forming an air gap adjacent a bottom source/drain region of a vertical transistor device and the resulting device that may avoid, or at least reduce, the effects of one or more of the problems identified above